From owner-freebsd-smp  Sun Dec 31 11:26:19 2000
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Date: Fri, 04 Jan 1980 21:30:19 +0100
From: "Josep M. Blanquer" <blanquer@cs.ucsb.edu>
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To: Matt Dillon <dillon@earth.backplane.com>
Cc: smp@FreeBSD.ORG
Subject: Re: getting processor's cacheline size?
References: <200012290623.eBT6NaJ03589@mass.osd.bsdi.com> <200012290636.eBT6a2m29328@earth.backplane.com> <20001229015117.F8848@cs.rice.edu> <200012291806.eBTI6jL32222@earth.backplane.com>
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Matt Dillon escribió:
> 
> :
> :On Thu, Dec 28, 2000 at 10:36:02PM -0800, Matt Dillon wrote:
> :>
> :>     16 bytes (128 bits) is typical.  I think 95% of all current processors
> :>     are either 16 bytes or 32 bytes.  ...
> :
> :You're on the low side:  Pentium II's and III's are 32 bytes.  Pentium 4's
> :(L1), Athlons, EV6's, and EV67's are 64 bytes.  The Pentium 4's L2 line size
> :is actually 128 bytes, but broken down into two 64 byte sectors.
> :(See page 1-18 of the manual at
> :http://developer.intel.com/design/pentium4/manuals/248966.htm.)
> :
> :Alan
> 
>   What can I say, I'm only a quarter micron engineer :-).
> 
> It occurs to me that we can probably detect the L1 and L2 cache line
> sizes on SMP systems dynamically by running a timing loop with two
> CPU's banging on a small segment of memory using locked instructions.
> By accessing memory N bytes apart on two cpu's (8, 16, 32, 64, 128, ...)
> and timing it we could determine the cache line size in a few milliseconds.

 I have a tool that detects (or tries to) several characteristics of 
the memory subsystem (including the line size) by just accessing memory 
in determined patterns and timing it...the tool runs on freebsd, 
solaris, linux...and Intel,Sparc and Alpha.
It´s not 100% but gets pretty good results. The actual implementation 
automatically detects cache sizes/levels, line sizes, associativity, 
"replacement policy" and write policy for both data and instruction 
caches as well as some TLB parameters. It has no multiprocessor design 
features, but it works well on them too.
It is probably something you can not use to detect parameters at
runtime,
(as someone pointed out) but it could be helpful at kernel config/make 
time...
I´m putting something toghether at http://steamboat.cs.ucsb.edu/mob 
but not all links are up yet. Not much information is available by now 
(a paper is submitted) but if anybody wants to give it a try feel free 
to contact me.

  Oh, BTW this is nothing commercial! 

 Josep M.


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From owner-freebsd-smp  Sun Dec 31 12:33:50 2000
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From: Matthew Jacob <mjacob@feral.com>
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To: "Josep M. Blanquer" <blanquer@cs.ucsb.edu>
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Subject: Re: getting processor's cacheline size?
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> I=B4m putting something toghether at http://steamboat.cs.ucsb.edu/mob=20
> but not all links are up yet. Not much information is available by now=20
> (a paper is submitted) but if anybody wants to give it a try feel free=20

Yeah:
The requested URL /mob/mob-1.0.tgz was not found on this server.<P>




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From owner-freebsd-smp  Sun Dec 31 22:17:39 2000
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Date: Fri, 04 Jan 1980 08:21:51 +0100
From: "Josep M. Blanquer" <blanquer@cs.ucsb.edu>
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Subject: Re: getting processor's cacheline size?
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Matthew Jacob escribió:
> 
> > I´m putting something toghether at http://steamboat.cs.ucsb.edu/mob
> > but not all links are up yet. Not much information is available by now
> > (a paper is submitted) but if anybody wants to give it a try feel free
> 
> Yeah:
> The requested URL /mob/mob-1.0.tgz was not found on this server.<P>

 That´s what I meant with "not all links up"... ;-) I wanted to prepare 
some more things before giving it away...but anyway...since it seems I´m
not going to have the time anytime soon, I grabbed one of the latest
distributions I could find and sticked it in the link. It should be 
functional but may have some configuration bugs...

  You should be able to download it now, any feedback would be
appreciated
(good or bad) since there´s only so much testing I can do...and besides
we
don´t have many different CPU´s to play with...

  Cheers,

  Josep M.


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