/* Generated automatically by the program `genattr-common'
   from the machine description file `md'.  */

#ifndef GCC_INSN_ATTR_COMMON_H
#define GCC_INSN_ATTR_COMMON_H

enum attr_got {GOT_UNSET, GOT_XGOT_HIGH, GOT_LOAD};
enum attr_jal {JAL_UNSET, JAL_DIRECT, JAL_INDIRECT};
enum attr_jal_macro {JAL_MACRO_NO, JAL_MACRO_YES};
enum attr_move_type {MOVE_TYPE_UNKNOWN, MOVE_TYPE_LOAD, MOVE_TYPE_FPLOAD, MOVE_TYPE_STORE, MOVE_TYPE_FPSTORE, MOVE_TYPE_MTC, MOVE_TYPE_MFC, MOVE_TYPE_MTLO, MOVE_TYPE_MFLO, MOVE_TYPE_IMUL, MOVE_TYPE_MOVE, MOVE_TYPE_FMOVE, MOVE_TYPE_CONST, MOVE_TYPE_CONSTN, MOVE_TYPE_SIGNEXT, MOVE_TYPE_EXT_INS, MOVE_TYPE_LOGICAL, MOVE_TYPE_ARITH, MOVE_TYPE_SLL0, MOVE_TYPE_ANDI, MOVE_TYPE_LOADPOOL, MOVE_TYPE_SHIFT_SHIFT};
enum attr_alu_type {ALU_TYPE_UNKNOWN, ALU_TYPE_ADD, ALU_TYPE_SUB, ALU_TYPE_NOT, ALU_TYPE_NOR, ALU_TYPE_AND, ALU_TYPE_OR, ALU_TYPE_XOR, ALU_TYPE_SIMD_ADD};
enum attr_mode {MODE_UNKNOWN, MODE_NONE, MODE_QI, MODE_HI, MODE_SI, MODE_DI, MODE_TI, MODE_SF, MODE_DF, MODE_TF, MODE_FPSW, MODE_V2DI, MODE_V4SI, MODE_V8HI, MODE_V16QI, MODE_V2DF, MODE_V4SF};
enum attr_dword_mode {DWORD_MODE_NO, DWORD_MODE_YES};
enum attr_qword_mode {QWORD_MODE_NO, QWORD_MODE_YES};
enum attr_sync_mem {SYNC_MEM_NONE, SYNC_MEM_0, SYNC_MEM_1, SYNC_MEM_2, SYNC_MEM_3, SYNC_MEM_4, SYNC_MEM_5};
enum attr_sync_oldval {SYNC_OLDVAL_NONE, SYNC_OLDVAL_0, SYNC_OLDVAL_1, SYNC_OLDVAL_2, SYNC_OLDVAL_3, SYNC_OLDVAL_4, SYNC_OLDVAL_5};
enum attr_sync_cmp {SYNC_CMP_NONE, SYNC_CMP_0, SYNC_CMP_1, SYNC_CMP_2, SYNC_CMP_3, SYNC_CMP_4, SYNC_CMP_5};
enum attr_sync_newval {SYNC_NEWVAL_NONE, SYNC_NEWVAL_0, SYNC_NEWVAL_1, SYNC_NEWVAL_2, SYNC_NEWVAL_3, SYNC_NEWVAL_4, SYNC_NEWVAL_5};
enum attr_sync_inclusive_mask {SYNC_INCLUSIVE_MASK_NONE, SYNC_INCLUSIVE_MASK_0, SYNC_INCLUSIVE_MASK_1, SYNC_INCLUSIVE_MASK_2, SYNC_INCLUSIVE_MASK_3, SYNC_INCLUSIVE_MASK_4, SYNC_INCLUSIVE_MASK_5};
enum attr_sync_exclusive_mask {SYNC_EXCLUSIVE_MASK_NONE, SYNC_EXCLUSIVE_MASK_0, SYNC_EXCLUSIVE_MASK_1, SYNC_EXCLUSIVE_MASK_2, SYNC_EXCLUSIVE_MASK_3, SYNC_EXCLUSIVE_MASK_4, SYNC_EXCLUSIVE_MASK_5};
enum attr_sync_required_oldval {SYNC_REQUIRED_OLDVAL_NONE, SYNC_REQUIRED_OLDVAL_0, SYNC_REQUIRED_OLDVAL_1, SYNC_REQUIRED_OLDVAL_2, SYNC_REQUIRED_OLDVAL_3, SYNC_REQUIRED_OLDVAL_4, SYNC_REQUIRED_OLDVAL_5};
enum attr_sync_insn1_op2 {SYNC_INSN1_OP2_NONE, SYNC_INSN1_OP2_0, SYNC_INSN1_OP2_1, SYNC_INSN1_OP2_2, SYNC_INSN1_OP2_3, SYNC_INSN1_OP2_4, SYNC_INSN1_OP2_5};
enum attr_sync_insn1 {SYNC_INSN1_MOVE, SYNC_INSN1_LI, SYNC_INSN1_ADDU, SYNC_INSN1_ADDIU, SYNC_INSN1_SUBU, SYNC_INSN1_AND, SYNC_INSN1_ANDI, SYNC_INSN1_OR, SYNC_INSN1_ORI, SYNC_INSN1_XOR, SYNC_INSN1_XORI};
enum attr_sync_insn2 {SYNC_INSN2_NOP, SYNC_INSN2_AND, SYNC_INSN2_XOR, SYNC_INSN2_NOT};
enum attr_accum_in {ACCUM_IN_NONE, ACCUM_IN_0, ACCUM_IN_1, ACCUM_IN_2, ACCUM_IN_3, ACCUM_IN_4, ACCUM_IN_5};
enum attr_type {TYPE_UNKNOWN, TYPE_BRANCH, TYPE_JUMP, TYPE_CALL, TYPE_LOAD, TYPE_FPLOAD, TYPE_FPIDXLOAD, TYPE_STORE, TYPE_FPSTORE, TYPE_FPIDXSTORE, TYPE_PREFETCH, TYPE_PREFETCHX, TYPE_CONDMOVE, TYPE_MTC, TYPE_MFC, TYPE_MTHI, TYPE_MTLO, TYPE_MFHI, TYPE_MFLO, TYPE_CONST, TYPE_ARITH, TYPE_LOGICAL, TYPE_SHIFT, TYPE_SLT, TYPE_SIGNEXT, TYPE_CLZ, TYPE_POP, TYPE_TRAP, TYPE_IMUL, TYPE_IMUL3, TYPE_IMUL3NC, TYPE_IMADD, TYPE_IDIV, TYPE_IDIV3, TYPE_MOVE, TYPE_FMOVE, TYPE_FADD, TYPE_FMUL, TYPE_FMADD, TYPE_FDIV, TYPE_FRDIV, TYPE_FRDIV1, TYPE_FRDIV2, TYPE_FABS, TYPE_FNEG, TYPE_FCMP, TYPE_FCVT, TYPE_FSQRT, TYPE_FRSQRT, TYPE_FRSQRT1, TYPE_FRSQRT2, TYPE_FMINMAX, TYPE_FRINT, TYPE_FCLASS, TYPE_DSPMAC, TYPE_DSPMACSAT, TYPE_ACCEXT, TYPE_ACCMOD, TYPE_DSPALU, TYPE_DSPALUSAT, TYPE_MULTI, TYPE_ATOMIC, TYPE_SYNCLOOP, TYPE_NOP, TYPE_GHOST, TYPE_MULTIMEM, TYPE_SIMD_DIV, TYPE_SIMD_FCLASS, TYPE_SIMD_FLOG2, TYPE_SIMD_FADD, TYPE_SIMD_FCVT, TYPE_SIMD_FMUL, TYPE_SIMD_FMADD, TYPE_SIMD_FDIV, TYPE_SIMD_BITINS, TYPE_SIMD_BITMOV, TYPE_SIMD_INSERT, TYPE_SIMD_SLD, TYPE_SIMD_MUL, TYPE_SIMD_FCMP, TYPE_SIMD_FEXP2, TYPE_SIMD_INT_ARITH, TYPE_SIMD_BIT, TYPE_SIMD_SHIFT, TYPE_SIMD_SPLAT, TYPE_SIMD_FILL, TYPE_SIMD_PERMUTE, TYPE_SIMD_SHF, TYPE_SIMD_SAT, TYPE_SIMD_PCNT, TYPE_SIMD_COPY, TYPE_SIMD_BRANCH, TYPE_SIMD_CMSA, TYPE_SIMD_FMINMAX, TYPE_SIMD_LOGIC, TYPE_SIMD_MOVE, TYPE_SIMD_LOAD, TYPE_SIMD_STORE};
enum attr_compact_form {COMPACT_FORM_ALWAYS, COMPACT_FORM_MAYBE, COMPACT_FORM_NEVER};
enum attr_cnv_mode {CNV_MODE_UNKNOWN, CNV_MODE_I2S, CNV_MODE_I2D, CNV_MODE_S2I, CNV_MODE_D2I, CNV_MODE_D2S, CNV_MODE_S2D};
enum attr_extended_mips16 {EXTENDED_MIPS16_NO, EXTENDED_MIPS16_YES};
enum attr_compression {COMPRESSION_NONE, COMPRESSION_ALL, COMPRESSION_MICROMIPS32, COMPRESSION_MICROMIPS};
enum attr_enabled {ENABLED_NO, ENABLED_YES};
enum attr_hazard {HAZARD_NONE, HAZARD_DELAY, HAZARD_HILO, HAZARD_FORBIDDEN_SLOT};
enum attr_can_delay {CAN_DELAY_NO, CAN_DELAY_YES};
enum attr_branch_likely {BRANCH_LIKELY_NO, BRANCH_LIKELY_YES};
enum attr_may_clobber_hilo {MAY_CLOBBER_HILO_NO, MAY_CLOBBER_HILO_YES};
enum attr_vr4130_class {VR4130_CLASS_MUL, VR4130_CLASS_MEM, VR4130_CLASS_ALU};
enum attr_ls2_turn_type {LS2_TURN_TYPE_ALU1, LS2_TURN_TYPE_ALU2, LS2_TURN_TYPE_FALU1, LS2_TURN_TYPE_FALU2, LS2_TURN_TYPE_UNKNOWN, LS2_TURN_TYPE_ATOMIC, LS2_TURN_TYPE_SYNCLOOP};
enum attr_sb1_fp_pipes {SB1_FP_PIPES_ONE, SB1_FP_PIPES_TWO};
#define INSN_SCHEDULING
#define DELAY_SLOTS 1

#endif /* GCC_INSN_ATTR_COMMON_H */
